Issue: 01/2019

Continuous cooperation: L3S and Infineon Technologies

Hardware platforms for driver assistance systems

More comfort and safety in road traffic – that is the aim of driver assistance systems. At present, such systems mainly have a supporting function, for example as distance or lane keeping assistants (partial automation). However, systems of the next generations (conditional to full automation) should take over the actual control of the vehicle. Numerous sensors have to be evaluated (ultrasound, laser, radar, cameras). In order to steer the vehicle safely through traffic, the control system must use these sensor data to reliably recognize and correctly interpret the traffic situation and its participants, i.e. other vehicles, pedestrians, but also road markings and traffic signs.

Convolutional Neural Networks (CNNs) are best suited for image recognition. These algorithms from the field of artificial intelligence even achieve better recognition rates than humans for certain tasks. However, the good quality of the results is bought with very high computing requirements. Modern CNNs, such as GoogLeNet, require billions of operations per input image. In order to further increase the detection rate, the trend is towards ever more powerful networks. The high parallelism of the network structure can be used to enable real-time processing at all (the result must be calculated in a maximum of 30 ms if one image per half meter is to be processed at 60 km/h): The network is divided into many small subtasks, which can often be calculated independently of each other. This allows a parallel and faster execution on several computing units. Especially modern graphics processors (GPUs) have moved into focus for CNNs, as numerous computing cores are available here. Due to their high energy absorption, however, such solutions are not suitable for use in vehicles. Mobile GPUs used in mobile phones, for example, are more energy-efficient, but also less powerful. Dedicated solutions, so-called AI accelerators, such as those offered by Intel with the Movidius Neural Compute Stick, are optimized for artificial intelligence algorithms, but show weaknesses in algorithms from other areas and thus only limited flexibility.

Guillermo Payá Vayá and his team are working together with Dream Chip Technologies from Garbsen on an effective and at the same time flexible solution: They are developing a new,  massively parallel and programmable processor architecture that is conceptually similar to a GPU, since many computing units can process parts of the actual task in parallel. In addition, the scientists are investigating the vertical vector concept for parallel data processing. With a smaller hardware it offers an enormously flexible processing of image data, which would have to be bought in GPUs only by further operations. With additional intelligent storage systems and an architecture optimized for the target technology, a fast, energy-efficient and flexible platform for image processing in the automotive sector is to be created.

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Prof. Dr.-Ing. Guillermo Payá Vayá

L3S member Guillermo Payá Vayá is junior professor at the Institute of Microelectronic Systems. His research includes ultra-power efficient processors and high-performance computing architectures.